By partitioning a flat memory into a hierarchical multi-bank memory, each memory bank of the multi-bank memory has, for example, localized and thereby shortened bit line pairs. Data to be applied to or received from a local bit line pair is transmitted through a global bit line pair across memory banks in a column. Due to a smaller loading of the global bit line pair compared to a bit line pair in the flat memory, a smaller access delay is incurred.
The multi-bank memory can be multi-port and allows multiple accessing operations per clock cycle, thereby increasing bandwidth of the multi-bank memory. To implement, for example, a dual-port memory bank, each memory cell can have an additional port added in addition to an existing read/write port. However, transistors and wires for implementing the additional port for each memory cell occupy additional area. Furthermore, a read-disturb-write situation or a write-disturb-write situation can arise, for example, when a write operation occurs at one port, and a dummy read operation resulted from a read operation or a write operation of another cell in the same row occurs at the other port simultaneously. In contrast, a dual-port memory bank can be implemented using single-port memory cells with the single port shared by two operations in a time division multiplexed manner. In this way, the area efficiency is higher and the read-disturb-write and write-disturb-write situations are prevented.